This invention relates to mixed-signal converters of the sigma-delta noise-shaping type and, more particularly, to mixed-signal converters that employ a multi-bit digital representation of the signal.
Recently, sigma-delta, or noise-shaping, mixed-signal converters have come into widespread use. This type of converter uses a relatively coarse quantizer, usually a single bit, embedded in a feedback loop. The feedback loop causes the large quantization noise of the quantizer to become shaped in the frequency domain such that the noise over a small range of the spectrum is very low. The out-of-band noise is then removed by a digital filter in the case of an analog-to-digital converter, or an analog filter in the case of a digital-to-analog converter. Sigma-delta converters exhibit excellent linearity and low quantization noise.
An important feature exploited by noise-shaping mixed-signal converters is oversampling of the signal. This provides bandwidth into which the quantization noise can be transferred, and subsequently filtered, if desired. This procedure improves the resolution of the digital representation of the signal, but only within a relatively small signal bandwidth compared with the sampling frequency. Because these converters are typically designed to have a very high input resolution (often 20 or more bits, or one part in 1 E+6) within their bandwidth specification, they are susceptible to imperfections, mismatch among circuit elements and thermal noise. Therefore, techniques that relax the design tolerances on specific electronic components are useful.
One of the primary obstacles in the design of noise-shaping mixed-signal converters is the problem of removing the large amount of out-of-band noise that is introduced by the digital modulator. Generally, this noise may be filtered, but the switched capacitor filter circuits typically used to accomplish this task are relatively expensive to build and may introduce nonlinear distortions. An alternative is to use multi-bit quantization, in which the digital word consists of more than a single bit. This approach can reduce the quantization noise directly.
An important element in multi-bit noise-shaping mixed-signal converters is the digital-to-analog converter (DAC) circuitry. In multi-bit digital-to-analog (D/A) converters, the DAC structure forms the desired output, whereas in multi-bit analog-to-digital (A/D) converters, the DAC constitutes an important element in the feedback loop. Typically, the DAC structure is configured by using a number N of nominally identical elements, each of which is a 1-bit DAC and provides a unit contribution (either 0 or 1) to a summing junction. The summed output forms the multi-bit DAC output.
Because of actual circuit nonidealities, such as mismatches between capacitors in an array of N capacitors in a switched capacitor array, the beneficial effects of the multi-bit feedback are lost due to the inherent nonlinearity caused by the mismatch. This nonlinearity directly leads to increased quantization noise and harmonic distortion within the signal bandwidth and can significantly degrade the performance of the converter.
A number of methods have been proposed and implemented for counteracting the effects of such mismatches. Many of these methods involve a form of randomization or rotation of the bits that specify which of the individual DACs are to be selected and which are to be deselected in a given clock cycle in an effort to even out, or to average, mismatches. Examples are disclosed in L. R. Carley, xe2x80x9cA Noise-Shaping Coder Topology for 15+ Bit Converters,xe2x80x9d IEEE J. Solid State Circuits, SC-24, No. 2, pages 267-273, April 1989; U.S. Pat. No. 5,406,283 issued Apr. 11, 1995 to Leung; and U.S. Pat. No. 5,856,799 issued Jan. 5, 1999 to Hamasaki et al. The main drawback of the disclosed methods is that they typically require many clock cycles to achieve the desired averaging, especially when the number of elements is large. This results in low frequency noise and may thereby degrade the performance in the passband of the converter.
U.S. Pat. No. 5,986,595 issued Nov. 16, 1999 to Lyden et al. attempts to address this problem by replacing the rotations with a more sophisticated sorting procedure that requires extra complexity in the circuitry. U.S. Pat. No. 5,684,482 issued Nov. 4, 1997 to Galton extends these ideas to handle the case of increased shaping order, but at the cost of introducing more complex switching logic as well as a nonlocal memory, which can be costly to implement in circuit layout. Moreover, Galton""s method works only for the case where the number of elements is equal to an integer power of 2.
U.S. Pat. No. 5,404,142 issued Apr. 4, 1995 to Adams et al. discloses a data-directed scrambling technique that relieves the burden of tight analog component matching. The quantized noise-shaped word is first converted to a xe2x80x9cthermometer codexe2x80x9d, where for an N-bit quantized word, 2N equally-weighted elements are used. In the thermometer code, the number of output bits set to one is equal to the input value. The fact that the output bits are equally-weighted allows dynamic mapping of digital input bits to analog elements of the digital-to-analog converter. By using an array of swapping elements whose state is controlled by the data itself, errors caused by analog mismatches can be manipulated, thereby shaping the noise in the output spectrum. Therefore, most of the noise energy can be moved out of the band of interest.
In the technique disclosed by Adams et al., each of the switching units, called a xe2x80x9c2xc3x972 swapper cell,xe2x80x9d has two inputs and two outputs, and these units are arranged in a xe2x80x9cbutterfly architecturexe2x80x9d similar to one commonly used in Fast Fourier Transform (FFT) algorithms. To further reduce the pattern tones, a randomizing pre-shifter can be used, as in the AD1853, a stereo multi-bit sigma-delta DAC sold by Analog Devices, Inc. The advantages of this method include its simple logic, which is local, and requires only 1-bit memories, and its efficiency: only (N/2) log2 N switching units are required for a thermometer encoder with N input levels. However, one restriction of this method is that it works only when the number of input levels is equal to an integer power of 2.
Accordingly, it is desirable to provide scrambling methods and apparatus for noise-shaping mixed-signal converters wherein one or more of the above drawbacks are overcome. For example, relaxing the constraint that the number of input levels to the multi-bit DAC has to be an integer power of 2 will allow more flexible designs when the desired accuracy calls for more elements but there is not enough chip area or power available to double the number of elements.
According to an aspect of the invention, a scrambling system comprises a rotator and a data-directed scrambler that can be used for arbitrary choices of N, the number of input levels. The rotator comprises an array of rotator cells, and the data-directed scrambler includes swapper cells and direct connections in appropriate places. An N-level equally-weighted digital signal is input to the rotator cells. The N outputs of the rotator cells are connected to the N inputs of the data-directed scrambler, and the N outputs of the data-directed scrambler are the final scrambled output. The operation of the scrambling system is controlled by a clock signal. At each successive clock cycle, the number of steps by which the inputs are shifted by the rotator may change by a given number. In addition, on each clock cycle, each swapper cell connects its two inputs to its two outputs, either directly or reversely, depending on the state of the two inputs and an additional state bit that represents the integrated difference of past swapper outputs.
Accordingly, apparatus is provided, in accordance with a first aspect of the invention, for processing N equally-weighted digital signals, where N is not an integer power of 2. The apparatus comprises a rotator for rotating the N equally-weighted digital signals in a sequence of rotator states in respective clock cycles to provide N rotated digital signals, and a data-directed scrambler having N inputs and N outputs for data-directed scrambling of the rotated digital signals to distribute the N equally-weighted digital signals to each of the N outputs of the scrambler such that the usage of the N outputs is dynamically balanced over a relatively small number of clock cycles. This allows one to manipulate the errors in the power spectrum.
The rotator may comprise circuit elements for advancing through a predetermined number of rotator states, wherein the N inputs of the rotator are shifted by a different number of steps with respect to the N outputs of the rotator in each of the rotator states. The circuit elements of the rotator may comprise rotator cells for performing a selected shift in response to a control signal and a sequencer for generating the control signal in response to a clock signal. The number N of digital signals may be of the form Mxc3x972k, where M is an odd integer and k is an integer. The rotator may have M rotator states. The N inputs of the rotator may be rotated (or shifted, modulo N) by 0, N/M, 2N/M, . . . (Mxe2x88x921) N/M steps in respective rotator states. Preferably, the predetermined number of rotator states is selected such that the frequency with which the rotator states are repeated is outside the signal band of the digital signals.
The rotator may comprise two or more sets of rotator cells connected in series between the N inputs and the N outputs of the rotator. Each of the sets of rotator cells passes its inputs directly to its outputs or shifts, modulo N, its inputs by a predetermined number of steps in response to a control signal. The rotator may further comprise a sequencer for providing control signals to the sets of rotator cells in response to a clock signal.
The data-directed scrambler may comprise one or more swapper cells and one or more direct connections interconnected to provide mutually exclusive selectable signal paths from the N inputs to the N outputs. Each of the swapper cells may comprise two input terminals to receive respective inputs and two output terminals to produce corresponding outputs, circuitry responsive to a select signal for connecting the two input terminals to the two output terminals, either directly or reversely, and logic for generating the select signal. The logic may comprise logic circuitry for storing the integrated difference of past swapper cell output signals, for determining a new value of the select signal based on the current two input values to the swapper cell and the stored integrated difference, and for updating the value of the stored integrated difference.
The data-directed scrambler may comprise two or more sets of elements connected in series between the N inputs and the N outputs of the data-directed scrambler. Each of the sets of elements may comprise swapper cells, or a combination of swapper cells and direct connections. The swapper cells may be connected in an FFT-like partial butterfly configuration. Direct connections are utilized in place of a swapper cell in each location of the partial butterfly configuration that does not require a swapper cell for swapping inputs to that location. Each of the swapper cells comprises circuitry responsive to a select signal for connecting two input terminals to two output terminals, either directly or reversely, and logic for generating the select signal.
According to another aspect of the invention, a method is provided for processing N equally-weighted digital signals, where N is not an integer power of two. The method comprises the steps of rotating the N equally-weighted digital signals in a sequence of rotator, states in respective clock cycles to provide N rotated digital signals, and data-directed scrambling of the N rotated digital signals in a data-directed scrambler having N inputs and N outputs to distribute the N equally-weighted digital signals to each of the N outputs of the scrambler such that the usage of the N outputs is dynamically balanced over a relatively small number of clock cycles.
According to a further aspect of the invention, apparatus is provided for processing N equally-weighted digital signals, where N is not an integer power of 2. The apparatus comprises a routing circuit, responsive to control signals and having N inputs and N outputs, for distributing the N equally-weighted digital signals to each of the N outputs such that the usage of the N outputs is dynamically balanced over a relatively small number of clock cycles, and a controller for generating the control signals in response to the digital signals and a sequencing signal.
According to a further aspect of the invention, a digital-to-analog converter is provided. The digital-to-analog converter comprises a code converter for converting a digital input to N equally-weighted digital signals, where N is not an integer power of 2, a rotator for rotating the N equally-weighted digital signals in a sequence of rotator states in respective clock cycles to provide N rotated digital signals, a data-directed scrambler having N inputs and N outputs for data-directed scrambling of the rotated digital signals to distribute the N equally-weighted digital signals to each of the N outputs of the scrambler such that the usage of the N outputs is dynamically balanced over a relatively small number of clock cycles, a digital-to-analog converter including N equally-weighted digital-to-analog converter elements for converting the scrambled digital signals to analog outputs, and a summing circuit for summing the outputs of the digital-to-analog converter elements to produce an analog output that represents the digital input.
According to a further aspect of the invention, an analog-to-digital converter is provided. The analog-to-digital converter comprises a summing unit for subtracting a feedback signal from an analog input signal and providing a summing unit output, a loop filter for receiving the summing unit output and providing a filter output signal, a multi-bit quantizer for providing a digital output in response to the filter output signal, and a digital-to-analog converter responsive to the digital output for providing the feedback signal to the summing unit. The digital-to-analog converter may be configured as described above. The digital output of the multi-bit quantizer represents the analog input signal.